41594B datasheet(31/372 Pages) MICROCHIP

31 / 372 page

 2011-2012 Microchip Technology Inc.

Preliminary

DS41594B-page 31

PIC12LF1840T48A

Bank 7

380h(1)

INDF0

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

381h(1)

INDF1

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

382h(1)

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

383h(1)

STATUS

—

—TO

ZDC

---1 1000 ---q quuu

384h(1)

FSR0L

Indirect Data Memory Address 0 Low Pointer

0000 0000 uuuu uuuu

385h(1)

FSR0H

Indirect Data Memory Address 0 High Pointer

0000 0000 0000 0000

386h(1)

FSR1L

Indirect Data Memory Address 1 Low Pointer

0000 0000 uuuu uuuu

387h(1)

FSR1H

Indirect Data Memory Address 1 High Pointer

0000 0000 0000 0000

388h(1)

BSR

—

BSR<4:0>

---0 0000 ---0 0000

389h(1)

WREG

Working Register

0000 0000 uuuu uuuu

38Ah(1)

PCLATH

—

Write Buffer for the upper 7 bits of the Program Counter

-000 0000 -000 0000

38Bh(1)

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

0000 000x 0000 000u

38Ch

—

Unimplemented

—

38Dh

—

Unimplemented

—

38Eh

—

Unimplemented

—

38Fh

—

Unimplemented

—

390h

—

Unimplemented

—

391h

IOCAP

—

IOCAP5

IOCAP4

IOCAP3

IOCAP2

IOCAP1

IOCAP0

--00 0000 --00 0000

392h

IOCAN

—

IOCAN5

IOCAN4

IOCAN3

IOCAN2

IOCAN1

IOCAN0

--00 0000 --00 0000

393h

IOCAF

—

IOCAF5

IOCAF4

IOCAF3

IOCAF2

IOCAF1

IOCAF0

--00 0000 --00 0000

394h

—

Unimplemented

—

395h

—

Unimplemented

—

396h

—

Unimplemented

—

397h

—

Unimplemented

—

398h

—

Unimplemented

—

399h

—

Unimplemented

—

39Ah

CLKRCON

CLKREN

CLKROE

CLKRSLR

CLKRDC<1:0>

CLKRDIV<2:0>

0011 0000 0011 0000

39Bh

—

Unimplemented

—

39Ch

MDCON

MDEN

MDOE

MDSLR

MDOPOL

MDOUT

—

MDBIT

0010 ---0 0010 ---0

39Dh

MDSRC

MDMSODIS

—

MDMS<3:0>

x--- xxxx u--- uuuu

39Eh

MDCARL

MDCLODIS

MDCLPOL MDCLSYNC

—

MDCL<3:0>

xxx- xxxx uuu- uuuu

39Fh

MDCARH

MDCHODIS MDCHPOL MDCHSYNC

—

MDCH<3:0>

xxx- xxxx uuu- uuuu

TABLE 3-7:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on all

other

Resets

Legend:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note

1: These registers can be addressed from any bank.

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