TIBPLS506AC

13

× 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER

SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303

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The configuration shown is a typical state-machine design with feedback signals sent off-chip. This external

feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest

path defining the clock period is the sum of the clock-to-output delay time and the setup time for the input or

1

tsu ) tpd CLK to Q

Internal

SR

Registers

Output

SR

Registers

Logic

Array

Next Device

CLK

Input

tsu

tpd

CLK to Q

Figure 4