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AD9518-2ABCPZ Fiches technique(PDF) 14 Page - Analog Devices |
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AD9518-2ABCPZ Fiches technique(HTML) 14 Page - Analog Devices |
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14 / 64 page ![]() AD9518-2 Data Sheet Rev. C | Page 14 of 64 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 35 36 34 33 32 31 30 29 28 27 26 25 AD9518-2 TOP VIEW (Not to Scale) PIN 1 INDICATOR CP STATUS CLK VCP REFMON LD BYPASS VS REF_SEL LF SYNC CLK OUT3 OUT2 VS VS VS_LVPECL VS_LVPECL OUT3 OUT2 NC GND VS GND NOTES 1. NC = NO CONNECT. 2. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. Pin Configuration Table 19. Pin Function Descriptions Pin No. Input/ Output Pin Type Mnemonic Description 1 O 3.3 V CMOS REFMON Reference Monitor (Output). This pin has multiple selectable outputs; see Table 44, Register 0x01B. 2 O 3.3 V CMOS LD Lock Detect (Output). This pin has multiple selectable outputs; see Table 44, Register 0x01A. 3 I Power VCP Power Supply for Charge Pump (CP). VS ≤ VCP ≤ 5.0 V. This pin is usually 3.3 V for most applications; but if a 5 V external VCXO is used, this pin should be 5 V. 4 O CP Charge Pump (Output). Connects to external loop filter. 5 O 3.3 V CMOS STATUS Status (Output). This pin has multiple selectable outputs; see Table 44, Register 0x017. 6 I 3.3 V CMOS REF_SEL Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor. 7 I 3.3 V CMOS SYNC Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor. 8 I Loop filter LF Loop Filter (Input). Connects to VCO control voltage node internally. This pin has 31 pF of internal capacitance to ground, which may influence the loop filter design for large loop bandwidths. 9 O Loop filter BYPASS This pin is for bypassing the LDO to ground with a capacitor. 10, 24, 25, 26, 35, 37, 43, 45 I Power VS 3.3 V Power Pins. 11 I Differential clock input CLK Along with CLK, this is the self-biased differential input for the clock distribution section. This pin can be left floating if internal VCO is used. 12 I Differential clock input CLK Along with CLK, this is the self-biased differential input for the clock distribution section. This pin can be left floating if internal VCO is used. |
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