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AD9518-2ABCPZ Fiches technique(PDF) 43 Page - Analog Devices

No de pièce AD9518-2ABCPZ
Description  6-Output Clock Generator with Integrated 2.2 GHz VCO
PDF  64 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9518-2ABCPZ Fiches technique(HTML) 43 Page - Analog Devices

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Data Sheet
AD9518-2
Rev. C | Page 43 of 64
CS
SCLK
SDIO
tHIGH
tLOW
tCLK
tS
tDS
tDH
tC
BIT N
BIT N + 1
Figure 51. Serial Control Port Timing Diagram—Write
Table 40. Serial Control Port Timing
Parameter
Description
tDS
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
tCLK
Period of the clock
tS
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
tC
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
tHIGH
Minimum period that SCLK should be in a logic high state
tLOW
Minimum period that SCLK should be in a logic low state
tDV
SCLK to valid SDIO and SDO (see Figure 49)



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