LTC3589 datasheet(36/50 Pages) LINER

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LTC3589/LTC3589-1/

LTC3589-2

3589fe

I2C OPERATION

I2C Interface

The LTC3589 communicates with a bus master using the

standard I2C 2-wire interface. The two bus lines, SDA and

SCL, must be HIGH when the bus is not in use. External

pull-up resistors or current sources, such as the LTC1694

SMBus accelerator, are required on these lines. The

LTC3589 is both a slave receiver and slave transmitter. The

I2C control signals, SDA and SCL are scaled internally to

the DVDD supply. DVDD should be connected to the same

power supply as the bus pull-up resistors.

The I2C port has an undervoltage lockout on the DVDD

pin. When DVDD is below approximately 1V, the I2C serial

port is reset to power-on states and registers are set to

default values.

I2C Bus Speed

The I2C port operates at speeds up to 400kHz. It has

built-in timing delays to ensure correct operation when

addressed from an I2C compliant master device. It also

contains input filters designed to suppress glitches should

the bus become corrupted.

I2C START and STOP Conditions

A bus master signals the beginning of communications

by transmitting a START condition. A START condition is

generated by transitioning SDA from HIGH to LOW while

SCL is HIGH. The master may transmit either the slave

write or the slave read address. Once data is written to the

LTC3589, the master may transmit a STOP condition that

commands the LTC3589 to act upon its new command

set. A STOP condition is sent by the master by transition-

ing SDA from LOW to HIGH while SCL is HIGH. The bus

it then free for communication with another I2C device.

I2C Byte Format

Each byte sent to or received from the LTC3589 must

be 8 bits long followed by an extra clock cycle for the

acknowledge bit. The data should be sent to the LTC3589

most significant bit (MSB) first.

I2C Acknowledge

The acknowledge signal is used for handshaking between

the master and the slave. When the LTC3589 is written to,

it acknowledges its write address and subsequent register

address and data bytes. When reading from the LTC3589,

it acknowledges its read address and 8-bit status byte.

An acknowledge pulse (active LOW) generated by the

LTC3589 lets the master know that the latest byte of

information was transferred. The master generates the

clock cycle and releases the SDA line (HIGH) during the

acknowledge clock cycle. The LTC3589 pulls down the SDA

line during the write acknowledge clock pulse so that it is

a stable LOW during the HIGH period of this clock pulse.

I2C Slave Address

The LTC3589 responds to factory programmed read and

write addresses. The write address is 0x68. The read ad-

dress is 0x69. The least significant bit of the address byte,

known as the read/write bit, is 0 when writing data to the

LTC3589 and 1 when reading from it.

OPERATION

Figure 20. LTC3589 I2C Serial Port Read Pattern

ACK

START

STOP

ADDRESS

5678

000

45678

123

5678

011

1001

45678

START

SDA

SCL

SUB ADDRESS

S7 S6

ADDRESS

DATA

R7 R6

R2 R1 R0

3589 F20

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