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LT3760

3760fc

applicaTions inForMaTion

Thermal Considerations

TheinternalpowerdissipationoftheLT3760comesfrom3

main sources: VIN quiescent current (IQ total), VIN current

for GATE switching (IGATE) and the LT3760 LED current

sources. Since the maximum operational VIN voltage is

40V, care should be taken when selecting the switching

frequency and type of external power MOSFET since the

current required from VIN for GATE switching is given by,

IGATE = fOSC • Qg

where Qg is the gate charge (at VGS = INTVCC) specified

for the MOSFET and fOSC is the programmed switching

frequency for the LT3760. A low Qg MOSFET should al-

ways be used when operating the LT3760 from high VIN

voltages. The internal junction temperature of the LT3760

can be estimated as:

TJ=TA+[VIN•(IQTOTAL+(fOSC•Qg))+(8•I(LEDX)•1.1V)]

•

θJA

where, TA is the ambient temperature for the LT3760

IQTOTALrepresentstheVINquiescentcurrentfortheLT3760

(not switching, PWM = 1.5V and CTRL = 0.1V) - illustrated

in the Typical Characteristics Graphs – plus the base cur-

rents of active channels (typically 8 • I(LED)/75).

θJA is

the thermal resistance of the package (28°C/W for the

28-pin TSSOP package).

Example : For a 12W LED driver application requiring 8

strings of 10 LEDs each driven with 40mA, VIN = 24V, fOSC

= 1MHz, Qg (at 7V VGS) = 15nC, I(LEDX) = 40mA, and an

85°C ambient temperature for the LT3760 IC, the LT3760

junction temperature can be approximated as:

TJ = 85°C + [24 • (9.5mA + (8 • 40mA/75) + (1MHz

• 15nC)) + (8 • 40mA • 1.1V)] • 34

= 85°C + [(24 • 28.8mA) + (320mA • 1.1V)] • 34

= 85°C + (0.691W + 0.35W) • 34

= 85°C + 35°C

TJ = 120°C

The exposed pad on the bottom of the package must be

soldered to the ground plane. The ground plane should

be connected to an internal copper ground plane with vias

placed directly under the package to spread out the heat

generated by the LT3760.

Circuit Layout Considerations

As with all switching regulators, careful attention must

be given to PCB layout and component placement to

achieveoptimalthermal,electricalandnoiseperformance.

The exposed pad of the LT3760 should be soldered to a

continuous copper ground plane underneath the device

to reduce die temperature and maximize the power capa-

bility of the IC. The signal ground (GND, pin 24) is down

bonded to the exposed pad near the RT and VC pins.

ISET, RT and VC components should be connected to an

area of ground copper connected to pin 24. The OVPSET

track should be kept away from fast moving signals and

not loaded with an external capacitor. GATE pin turn off

currents escape through a downbond to the exposed pad

and exit the PGND, pin 10. This area of copper and pin

10 should be the power ground (PGND) connection for

the inductor input capacitor, INTVCC capacitor and output

capacitor. A separate bypass capacitor for the VIN pin of

the IC may be required close the VIN pin and connected to

the copper area associated with signal ground, pin 24. To

minimize MOSFET peak current sensing errors the sense

resistor(RS)shouldhaveKelvinconnectionstotheSENSE

pin and the power ground copper area near the pin. The

MOSFET drain rise and fall times are designed to be as

short as possible for maximum efficiency. To reduce the

effects of both radiated and conducted noise, the area of

the copper trace for the MOSFET drain should be kept as

small as possible. Use a ground plane under the switching

regulator to minimize interplane coupling. The Schottky

diode and output capacitor should be placed as close as

possible to the drain node to minimize this high switching

frequency path.

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