AD9577BCPZ-R7 datasheet(38/44 Pages) AD

No de pièce	AD9577BCPZ-R7

Description	Clock Generator with Dual PLLs

PDF	44 Pages

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Fabricant	AD [Analog Devices]

Site Internet	http://www.analog.com

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38 / 44 page

AD9577

Data Sheet

Rev. 0 | Page 38 of 44

I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION

SLAVE ADDRESS [6:0]

R/W

CTRL

0 = WR

1 = RD

Figure 44. Slave Address Configuration

S SLAVE ADDR, LSB = 0 (WR) A(S)

A(S)

DATA

SUB ADDR

A(S) P

DATA

Figure 45. I2C Write Data Transfer

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(M) = LACK OF ACKNOWLEDGE BY MASTER

SLAVE ADDR, LSB = 0 (WR)

SLAVE ADDR, LSB = 1 (RD)

A(S)

SUB ADDR

A(S) DATA A(M)

DATA

A(M)

Figure 46. I2C Read Data Transfer

START BIT

STOP BIT

ACK

SLADDR[4:0]

SLAVE ADDRESS

SUB ADDRESS

DATA

SUB ADDR[6:1]

DATA[6:1]

SCL

SDA

Figure 47. I2C Data Transfer Timing

tBUF

SDA

SCL

tLOW

tHD;STA

tHD;DAT

tSU;DAT

tHIGH

tSU;STA

tSU;STO

tHD;STA

Figure 48. I2C Port Timing Diagram

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