SIC403 datasheet(13/25 Pages) VISHAY

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Vishay Siliconix

SiC403

Document Number: 66550

S11-1638-Rev. B, 15-Aug-11

www.vishay.com

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Note that because the low-side MOSFET with low RDS(ON) is

used

for

current

sensing,

the

PCB

layout,

solder

connections, and PCB connection to the LX node must be

done carefully to obtain good results. Refer to the layout

guidelines for information.

Soft-Start of PWM Regulator

SiC403 has a programmable soft-start time that is controlled

by an external capacitor at the SS pin. After the controller

meets both UVLO and EN/PSV thresholds, the controller has

an internal current source of 2.75 µA flowing through the

SS pin to charge the capacitor. During the start up process,

50 % of the voltage at the SS pin is used as the reference for

the FB comparator. The PWM comparator issues an on-time

pulse when the voltage at the FB pin is less than 50 % of the

SS pin. As result, the output voltage follows the SS start

voltage.

The

output

voltage

reaches

and

maintains

regulation when the soft start voltage is > 1.5 V. The time

between the first LX pulse and when VOUT meets regulation

is the soft start time (tSS). The calculation for the soft-start

time is shown by the following equation:

Power Good Output

The power good (PGOOD) output is an open-drain output

which requires a pull-up resistor. When the output voltage is

10 % below the nominal voltage, PGOOD is pulled low. It is

held low until the output voltage returns above - 8 % of nom-

inal. PGOOD is held low during start-up and will not be allowed

to transition high until soft-start is completed (when VFB

reaches 750 mV) and typically 2 ms has passed.

PGOOD will transition low if the VFB pin exceeds + 20 % of

nominal, which is also the over-voltage shutdown threshold

(900 mV). PGOOD also pulls low if the EN/PSV pin is low

when VDD is present.

Output Over-Voltage Protection

Over-voltage protection becomes active as soon as the

device is enabled. The threshold is set at 750 mV + 20 %

(900 mV). When VFB exceeds the OVP threshold, DL latches

high and the low-side MOSFET is turned on. DL remains

high and the controller remains off , until the EN/PSV input is

toggled or VDD is cycled. There is a 5 µs delay built into the

OVP detector to prevent false transitions. PGOOD is also low

after an OVP event.

Output Under-Voltage Protection

When VFB falls 25 % below its nominal voltage (falls to

562.5 mV) for eight consecutive clock cycles, the switcher is

shut off and the DH and DL drives are pulled low to tristate

the MOSFETs. The controller stays off until EN/PSV is

toggled or VDD is cycled.

VDD UVLO, and POR

Under-voltage lock-out (UVLO) circuitry inhibits switching

and tri-states the DH/DL drivers until VDD rises above 3.9 V.

An internal Power-On Reset (POR) occurs when VDD

exceeds 3.9 V, which resets the fault latch and soft-start

counter to prepare for soft-start. The SiC403 then begins a

soft-start cycle. The PWM will shut off if VDD falls below

3.6 V.

LDO Regulator

The device features an integrated LDO regulator with a fixed

output voltage of 5 V. There is also an enable pin (ENL) for

the LDO that provides independent control. The LDO voltage

can also be used to provide the bias voltage for the switching

regulator.

A minimum capacitance of 1 µF referenced to AGND is

normally required at the output of the LDO for stability. If the

LDO is providing bias power to the device, then a minimum

0.1 µF capacitor referenced to AGND is required, along with

a minimum 1 µF capacitor referenced to PGND to filter the

gate drive pulses. Refer to the layout guidelines section.

LDO Start-up

Before start-up, the LDO checks the status of the following

signals to ensure proper operation can be maintained.

1. ENL pin

2. VLDO output

3. VIN input voltage

When the ENL pin is high and VIN is above the UVLO point,

the LDO will begin start-up. During the initial phase, when the

LDO output voltage is near zero, the LDO initiates a

current-limited start-up (typically 85 mA) to charge the output

capacitor. When VLDO has reached 90 % of the final value

(as sensed at the FBL pin), the LDO current limit is increased

to ~ 200 mA and the LDO output is quickly driven to the

nominal value by the internal LDO regulator.

LDO Switchover Function

The SiC403 includes a switch-over function for the LDO. The

switch-over function is designed to increase efficiency by

using the more efficient DC/DC converter to power the LDO

output, avoiding the less efficient LDO regulator when

possible. The switch-over function connects the VLDO pin

directly to the VOUT pin using an internal switch. When the

switch-over is complete the LDO is turned off, which results

in a power savings and maximizes efficiency. If the LDO

output is used to bias the SiC403, then after switch-over the

device is self-powered from the switching regulator with the

LDO turned off.

The switch-over logic waits for 32 switching cycles before it

starts the switch-over. There are two methods that determine

the switch-over of VLDO to VOUT.

SS = CSS x

1.5 V

2.75 μA

Figure 9 - LDO Start-Up

Constant current startup

VVLDO final

90 % of VVLDO final

Voltage regulating with

~ 200 mA current limit

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