SIC403 datasheet(11/25 Pages) VISHAY

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Vishay Siliconix

SiC403

Document Number: 66550

S11-1638-Rev. B, 15-Aug-11

www.vishay.com

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

The maximum RTON value allowed is shown by the following

equation.

VOUT Voltage Selection

The switcher output voltage is regulated by comparing VOUT

as seen through a resistor divider at the FB pin to the internal

750 mV reference voltage, see figure 3.

As the control method regulates the valley of the output ripple

voltage, the DC output voltage VOUT is off set by the output

ripple according to the following equation.

VOUT = 0.75 x (1 + R1/R2) + VRIPPLE/2

Enable and Power-Save Inputs

The EN/PSV and ENL inputs are used to enable or disable

the switching regulator and the LDO.

When EN/PSV is low (grounded), the switching regulator is

off and in its lowest power state. When off, the output of the

switching regulator soft-discharges the output into a 15



internal resistor via the VOUT pin.

When EN/PSV is allowed to float, the pin voltage will float to

1.5 V. The switching regulator turns on with power-save

disabled and all switching is in forced continuous mode.

When EN/PSV is high (above 2 V), the switching regulator

turns on with ultra-sonic power-save enabled. The SiC403

ultra-sonic power-save operation maintains a minimum

switching frequency of 25 kHz, for applications with stringent

audio requirements.

The ENL input is used to control the internal LDO. This input

serves a second function by acting as a VIN UVLO sensor for

the switching regulator.

The LDO is off when ENL is low (grounded). When ENL is a

logic high but below the VIN UVLO threshold (2.6 V typical),

then the LDO is on and the switcher is off. When ENL is

above the VIN UVLO threshold, the LDO is enabled and the

switcher is also enabled if the EN/PSV pin is not grounded.

Forced Continuous Mode Operation

The SiC403 operates the switcher in Forced Continuous

Mode (FCM) by floating the EN/PSV pin (see figure 4). In this

mode one of the power MOSFETs is always on, with no

intentional dead time other than to avoid cross-conduction.

This feature results in uniform frequency across the full load

range with the trade-off being poor efficiency at light loads

due to the high-frequency switching of the MOSFETs.

Ultrasonic Power-Save Operation

The SiC403 provides ultra-sonic power-save operation at

light loads, with the minimum operating frequency fixed at

25 kHz. This is accomplished using an internal timer that

monitors the time between consecutive high-side gate

pulses.

If the time exceeds 40 µs, DL drives high to turn the low-side

MOSFET on. This draws current from VOUT through the

inductor, forcing both VOUT and VFB to fall. When VFB drops

to the 750 mV threshold, the next DH on-time is triggered.

After the on-time is completed the high-side MOSFET is

turned off and the low-side MOSFET turns on, the low-side

MOSFET remains on until the inductor current ramps down

to zero, at which point the low-side MOSFET is turned off.

Figure 3 - Output Voltage Selection

Rton_MAX =

VIN_MIN

15 µA

VOUT

To FB pin

Figure 4 - Forced Continuous Mode Operation

Figure 5 - Ultrasonic power-save Operation

FB ripple

voltage (VFB)

Inductor

current

DC load current

FB threshold

(750 mV)

On-time

(tON)

DH on-time is triggered when

VFB reaches the FB threshold

DL drives high when on-time is completed.

DL remains high until VFB falls to the FB threshold.

FB ripple

voltage (VFB)

Inductor

current

(0A)

FB threshold

(750 mV)

On-time

(tON)

DH on-time is triggered when

VFB reaches the FB threshold

After the 40 µs time-out, DL drives high if VFB

has not reached the FB threshold.

minimum fSW ~ 25 kHz

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