SM5K3 datasheet(22/28 Pages) SHARP

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SM5K3/SM5K4/SM5K5

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• Divider

The divider consists of 15 divided-by-two dividers,

providing 2 (fSYS/27, fSYS/215) of 4 count clocks that

are fed to the counter RA from the system clock.

Its configuration is shown below. The divider can

be cleared by using the DR instruction.

• Oscillator mask option

Selection of type of oscillator, ceramic or crystal, is

made by mask option.

System clock

(fSYS)

Main clock

(fOSC)

OSCIN

OSCOUT

( System clock )

1111

111

2222

222

Divider (can be cleared by DR instruction)

System clock generator (divided-by-two main clock)

fSYS

fSYS/2

Fig. 12

Main Clock and System Clock

Fig. 13

System Clock Generator and Divider

System Clock Generator and Dividers

• System clock generator

The system clock is the divided-by-two main clock

applied through OSCIN and OSCOUT (See Fig. 12).

The system clock generator is shown in Fig. 13.

One system clock cycle period is equal to one

instruction execution time when the instruction

consists of 1 word. When the ceramic oscillator

runs at 400 kHz, the system clock fsys is 200 kHz.

This means that the instruction execution time is 5

µs/word. Using a 32.768 kHz crystal oscillator

generates 16.384 kHz fsys and the instruction

execution time is 61 µs/word. The system clock

can be used as count input pulse to the timer.

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