Device family overview

MPC5602D Microcontroller Product Brief, Rev. 3.1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

17

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6 chip select lines for DSPI_0 and 5 for DSPI_1, depending on package and pin multiplexing, to

enable 64 external devices to be selected using external muxing from a single DSPI

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Up to 8 transfer types, independently configurable for each DSPI using the clock and transfer

attributes registers

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Chip select strobe available as alternate function on one of the chip select pins for deglitching

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FIFOs for buffering up to 4 transfers on the transmit and receive side

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General purpose I/O functionality on pins when not used for SPI

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Queueing operation possible through use of eDMA

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32-bit serialization of data enabling virtual GPIO ports on two DSPI modules

3.5.10

Controller Area Network Module (FlexCAN)

MPC5602D devices have one FlexCAN module. Features include:

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Compliant with CAN protocol specification, version 2.0B active

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32 mailboxes

— Mailboxes configurable while module remains synchronized to CAN bus

— Each mailbox configurable as transmit or receive

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Transmit features

— Supports configuration of multiple mailboxes to form message queues of scalable depth

— Arbitration scheme according to message ID or message buffer number

— Internal arbitration to guarantee no inner or outer priority inversion

— Transmit abort procedure and notification

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Receive features

— 2 mailboxes filtered

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Programmable clock source

— System clock

— Direct oscillator clock to avoid PLL jitter

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Listen-only mode capabilities

3.5.11

System clocks and clock generation

The following list summarizes the system clock and clock generation on the MPC5602D:

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System clock can be derived from the following sources

— External crystal oscillator

—FMPLL

— 16 MHz fast internal RC oscillator

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Programmable output clock divider of system clock (

1, 2, 4)

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Separate programmable peripheral bus clock divider ratio (

1, 2, 4) applied to system clock

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Frequency modulated phase-locked loop (FMPLL)