Device family overview

MPC5602D Microcontroller Product Brief, Rev. 3.1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

11

STANDBY mode halts the clock to the entire device and turns off the power to the majority of the chip to

offer the lowest power consumption mode.

The device can be woken up from STANDBY mode by any of up to 18 external wakeup pins, a reset, or

from a periodic wakeup using a low power oscillator. If required by the user, it is possible to enable the

internal 16 MHz or 128 kHz RC oscillator.

In STANDBY mode, the contents of the cores, on-chip peripheral registers and potentially some of the

volatile memory are not held. STANBDY mode retains 16 KB of the SRAM

A fast wakeup using the on-chip 16 MHz internal RC oscillator allows rapid execution from SRAM on

exit from low power modes. This oscillator supports low speed code execution and clocking of peripherals

through selection as the system clock, and it can be used as the PLL input clock source to provide fast

startup without the external oscillator delay.

In low power modes, the internal 16 MHz RC oscillator also supports the operation of ADCs.

Additionally, up to 18 external wakeup pins are available for wakeup, and a fast startup internal voltage

regulator provides a rapid exit from low power modes.

3.4

Chip-level features

On-chip modules available within the family include the following features:

•

Single issue, 32-bit CPU core complex (e200z0h)

— Compliant with the Power Architecture embedded category

— Includes an instruction set enhancement allowing variable length encoding (VLE) for code size

footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is

possible to achieve significant code size footprint reduction.

•

Up to 256 KB on-chip Code Flash supported with the Flash controller

•

64 KB on-chip Data Flash

•

Up to 16 KB on-chip SRAM

•

Interrupt controller (INTC) capable of handling 155 selectable-priority interrupt sources

•

Frequency modulated phase-locked loop (FMPLL)

•

Crossbar switch architecture for concurrent access to peripherals, Flash, or SRAM from multiple

bus masters

•

16-channel eDMA controller with multiple transfer request sources using DMAMUX

•

Boot assist module (BAM) supports internal Flash programming via a serial link (CAN or SCI)

•

Timer supports input/output channels providing a range of 16-bit input capture, output compare,

and pulse width modulation functions (eMIOS-lite)

•

One 12-bit analog-to-digital converters (ADC)

•

Cross Trigger Unit (CTU) to enable synchronization of ADC conversions with a timer event from

the eMIOS or from the PIT

•

2 serial peripheral interface (DSPI) modules

•

3 serial communication interface (LINFlex) modules