M41T83RM6F datasheet(33/61 Pages) STMICROELECTRONICS

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M41T82-M41T83

Clock operation

Doc ID 12578 Rev 12

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Figure 20.

Crystal isolation example

Substrate pad should be tied to VSS.

3.5

Setting the alarm clock registers

Codes not listed in the table default to the once-per-second mode to quickly alert the user of

an incorrect alarm setting. When the clock information matches the alarm clock settings

based on the match criteria defined by RPTx5–RPTx1 (x = 1 for alarm 1 or 2 for alarm 2),

the alarm flag, AFx, is set. Reading the flags register clears the alarm flags. A subsequent

read of the flags register is necessary to see that the value of the alarm flag has been reset

to 0.

M41T83 interrupts on alarm

In the M41T83, for alarm 1, setting the alarm interrupt enable, A1IE, allows an interrupt

output to be asserted upon AF1 being set provided that other configuration bits are set

accordingly (see Section 3.14 for more information on the IRQ/FT/OUT output).

Likewise for alarm 2, with A2IE set, IRQ2 will be asserted upon AF2 going high. To disable

either of the alarms, write a 0 to the alarm date registers and to the RPTx5–RPTx1 bits.

Note:

If the address pointer is allowed to increment to the flag register address, or the last address

written is “Alarm Seconds,” the address pointer will increment to the flag address, and an

alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to

a different address.

Alarm IRQ outputs are de-asserted when the alarm flags are cleared by reading the flags

The IRQ1/FT/OUT pin can also be activated in the battery backup mode. This requires the

ABE bit (alarm in backup enable) to be set (see Section 3.14.2: Backup mode for additional

conditions which apply). Once an interrupt is asserted in backup mode, it will remain true

until VCC is restored and a subsequent read of the flags register occurs.

AI11814

Crystal

XI XO

VSS

Local Grounding

Plane (Layer 2)

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