M41T83RM6F datasheet(31/61 Pages) STMICROELECTRONICS

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M41T82-M41T83

Clock operation

Doc ID 12578 Rev 12

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The on-chip capacitance can be calculated as follows:

where ACS is the sign.

For example:

●

CLOAD (12h = x0000000) = 12.5 pF

●

CLOAD (12h =11001000) = 3.5 pF (sign is negative)

●

CLOAD (12h = 00100111) = 17.4 pF

With the analog calibration adjusted to its lowest value, the oscillator will see a minimum of

3.5 pF load capacitance as shown on the bottom row of Table 7.

Note:

These are typical values, and the total load capacitance seen by the crystal will include

approximately 1-2 pF of package and board capacitance in addition to the analog calibration

Any invalid value of analog calibration will result in the default capacitance of 25 pF.

The combination of analog and digital trimming can give up to –93 to +156 ppm of the total

adjustment.

Figure 18 represents a typical curve of clock ppm adjustment versus the analog calibration

value. This curve may vary with different crystals, so it is good practice to evaluate the

crystal to be used with an M41T8x device before establishing the adjustment values for the

application in question.

Figure 18.

Clock accuracy vs. on-chip load capacitance

[]pF

)

decimal

value

(

ACS

CLOAD

⋅

ai13906

DECREASING LOAD CAP.

-20.0

0.0

20.0

40.0

60.0

80.0

100.0

-5.0

-18.0 -15.0

-10.0

0.0

5.0

9.75

Analog Calibration

Value, AC,

OFFSET TO

CXI, CXO (pF)

NET EQUIV. LOAD

CAP., C LOAD, (pF)

3.5

5.0

7.5

12.5

17.4

0xC8 0xBC

0xA8

0x94

0x00

0x14

0x27

INCREASING LOAD CAP.

SLOWER

FASTER

Crystal

Oscillator

CXO

CXI

CLOAD =

CXI + CXO

CXI * CXO

On-Chip

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