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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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PSD813F2 Fiches technique(PDF) 25 Page - STMicroelectronics |
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PSD813F2 Fiches technique(HTML) 25 Page - STMicroelectronics |
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25 / 128 page  PSD8XXFX PSD register description and address offset Doc ID 7833 Rev 7 25/128 Mask macrocells AB 22 22 Blocks writing to the Output macrocells AB Mask macrocells BC 23 23 Blocks writing to the Output macrocells BC Primary Flash Protection C0 Read only – Primary Flash Sector Protection Secondary Flash memory Protection C2 Read only – PSD Security and Secondary Flash memory Sector Protection JTAG Enable C7 Enables JTAG port PMMR0 B0 Power Management register 0 PMMR2 B4 Power Management register 2 Page E0 Page register VM E2 Places PSD memory areas in program and/or data space on an individual basis. 1. Other registers that are not part of the I/O ports. Table 8. Register address offset (continued) Register name Port A Port B Port C Port D Other (1) Description |
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