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Low Power Features

Datasheet

2.1.1

Core Low-Power States

2.1.1.1

C0 State

This is the normal operating state for the core of the Celeron M processor.

2.1.1.2

C1/AutoHALT Powerdown State

C1/AutoHALT is a low power state entered when the processor core executes the HALT

instruction. The processor core will transition to the C0 state upon the occurrence of

SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the

processor to immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the IA-32 Intel® Architecture Software

Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the AutoHALT

Powerdown state. When the system deasserts the STPCLK# interrupt, the processor

will return execution to the HALT state.

While in AutoHALT Powerdown state the Celeron M processor will process only the bus

snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to

process the snoop and then return to the AutoHALT Powerdown state.

Figure 2.

Core Low Power States

†

Stop

Grant

Core state

break

P_LVL2 or

MWAIT(C2)

†

Core

state

break

P_LVL3 or

MWAIT(C3)

C1/

MWAIT

Core state

break

MWAIT(C1)

C1/Auto

Halt

Halt break

HLT instruction

STPCLK#

de-asserted

STPCLK#

asserted

STPCLK#

de-asserted

STPCLK#

asserted

STPCLK#

de-asserted

STPCLK#

asserted

halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)

† — STPCLK# assertion and de-assertion have no affect if a core is in C2, or C3.

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