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ADR 6

Transmit control 0

Bit

Description

Name

CR6B[0-2]

0-2

Set value for transmit bit counter (bit 0-2) which is loaded in the

transmit counter when the synchronization pulse is active.

CR6B3

Transmit Test data Polarity

Outputs are active low if bit is at “0”

CR6B4

External Transmit Channel Parity Type

0 : Even

1 : Odd

CR6B5

Enable External Transmit Channel Parity Input.

The internally generated channel parity signal is compared

with the signal at the channel parity input if this register bit is

set to “1”. For signalling, the parity-value on the parity input is

ignored, because it is generated internally.

CR6B6

Enable Internal Signalling Stack.

If set to “1” the two-byte stacks for receive and transmit

signaling data (timeslot 16) are enabled. Access to the TS16

Signalling Stack is possible via µP interface or by means of

DMA. The RREQ and XREQ signals can be used either as

interrupts or as DMA request signals. For DMA transfer the

ACKNLQ pin should be used for direct access to the stacks.

CR6B7

Transmit Data Output Polarity

Bit at “1” : Dual rail outputs are active high, optical output

is active low

Bit at “0” : Dual rail outputs are active low, optical output is

active high

ADR 7

Transmit Control 1

Bit

Description

Name

CR7B[0-5]

0-5

Set value for timeslot which is loaded into the transmit counter

when the synchronization pulse is active

CR7B6

Mark CRC Alarm (Bit at "1" - Enable Alarm Source)

CR7B7

Select System Clock

0 : SCLK = 4.096MHz

1 : SCLK = 8.192MHz

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