6 / 10 page
2-104
RF2131
Rev B4 010417
2
Application Schematic 1
Optimized for Efficiency at 4.8V
This schematic defines the optimum configuration for maximum efficiency at 4.8V. Under these conditions, as can be
seen in the data plots, the power drops at 4.0 V. Over 70% power-added efficiency can be achieved at +30.8 dBm with
4.8 V and +8dBm input level with this implementation.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BIAS
100 nF
100 pF
RF IN
10 nF
V
CC
10 nF
100 pF
10 nH
4.7 pF
10 nH
4.7 pF
2.7 nH
100 pF
RF OUT
5.6 pF
33 pF
V
CC
100 pF
100 nF
33 pF
V
CC
0.200"
VPC
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
