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CMPWR150SF Fiches technique(PDF) 11 Page - ON Semiconductor |
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CMPWR150SF Fiches technique(HTML) 11 Page - ON Semiconductor |
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11 / 15 page ![]() CMPWR150 Rev. 3 | Page 11 of 15 | www.onsemi.com LoadStep.bmp Figure 10. Load Step Response Line Step Response. Figure 11 shows the output response of the regulator to a V CC line voltage transient between 4.5V and 5.5V (1Vpp as shown on Ch1). The load condition during this test is 5mA. The output response produces less than 10mV of disturbance on both edges indicating a line rejection of better than 40dB at high frequencies. V OUT offset = 3.3V LineStep.bmp Figure 11. Line Step Response |
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