STM8S207MBT3 datasheet(16/103 Pages) STMICROELECTRONICS

16 / 103 page

Product overview

STM8S207xx, STM8S208xx

16/103

Doc ID 14733 Rev 9

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data

EEPROM memory in ICP mode (and debug mode). Once the read-out protection is

activated, any attempt to toggle its status triggers a global erase of the program and data

memory. Even if no protection can be considered as totally unbreakable, the feature

provides a very high level of protection for a general purpose microcontroller.

4.5

Clock controller

The clock controller distributes the system clock (fMASTER) coming from different oscillators

to the core and the peripherals. It also manages clock gating for low power modes and

ensures clock robustness.

Features

●

Clock prescaler: To get the best compromise between speed and current

consumption the clock frequency to the CPU and peripherals can be adjusted by a

programmable prescaler.

●

Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register. The clock signal is not switched until the new clock

source is ready. The design guarantees glitch-free switching.

●

Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

●

Master clock sources: Four different clock sources can be used to drive the master

clock:

–

1-24 MHz high-speed external crystal (HSE)

–

Up to 24 MHz high-speed user-external clock (HSE user-ext)

–

16 MHz high-speed internal RC oscillator (HSI)

–

128 kHz low-speed internal RC (LSI)

●

Startup clock: After reset, the microcontroller restarts by default with an internal 2

MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the

application program as soon as the code execution starts.

●

Clock security system (CSS): This feature can be enabled by software. If an HSE

clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS

and an interrupt can optionally be generated.

●

Configurable main clock output (CCO): This outputs an external clock for use by the

application.

Table 3.

Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit

Peripheral

clock

Bit

Peripheral

clock

Bit

Peripheral

clock

Bit

Peripheral

clock

PCKEN17

TIM1

PCKEN13

UART3

PCKEN27

beCAN

PCKEN23

ADC

PCKEN16

TIM3

PCKEN12

UART1

PCKEN26

Reserved

PCKEN22

AWU

PCKEN15

TIM2

PCKEN11

SPI

PCKEN25

Reserved

PCKEN21

Reserved

PCKEN14

TIM4

PCKEN10

I2C

PCKEN24

Reserved

PCKEN20

Reserved

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