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STM8S207MB Fiches technique(PDF) 77 Page - STMicroelectronics |
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STM8S207MB Fiches technique(HTML) 77 Page - STMicroelectronics |
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77 / 103 page ![]() STM8S207xx, STM8S208xx Electrical characteristics Doc ID 14733 Rev 9 77/103 Figure 34. Typical NRST pull-up resistance vs VDD @ 4 temperatures Figure 35. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures The reset network shown in Figure 36 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 37. Otherwise the reset is not taken into account internally. Figure 36. Recommended reset pin protection 30 35 40 45 50 55 60 2.5 3 3.5 4 4.5 5 5.5 6 -40˚C 25˚C 85˚C 125˚C VDD [V] 0 20 40 60 80 100 120 140 01 234 5 6 V DD [V] -40˚C 25˚C 85˚C 125˚C ai15069 0.01µF External reset circuit STM8 Filter RPU VDD Internal reset NRST (optional) |
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