74LVC74A_6

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 06 — 4 June 2007

7 of 16

NXP Semiconductors

74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

[4]

N = number of inputs switching

11. AC waveforms

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 7.

The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,

the nCP to nD hold times, and the maximum frequency

mna422

GND

GND

nCP input

nD input

nQ output

nQ output