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WM8148 Fiches technique(PDF) 9 Page - Wolfson Microelectronics plc

No de pièce WM8148
Description  12-bit/12MSPS CCD/CIS Analogue Front End/Digitiser
PDF  43 Pages
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Fabricant  WOLFSON [Wolfson Microelectronics plc]
Site Internet  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8148 Fiches technique(HTML) 9 Page - Wolfson Microelectronics plc

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WM8148
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
9
RESET LEVEL CLAMP
MCLK
VSMP
RLC = 1
RLC = 0
t
RLCSU
t
RLCH
Figure 3 Reset Level Clamp Control Timing
CL
CL
CL
CL
MCLK
MODE 8-13
SMALL = 0
MODE 8-13
SMALL = 1
MODE 0-5
SMALL = 0
MODE 0-5
SMALL = 1
OFF
O N
OFF
OFF
O N
OFF
OFF
O N
OFF
OFF
O N
OFF
t
PER
t
RLCPD
t
RLCPD
t
RLCPD
t
RLCPD
t
RLCPD
t
RLCPD
t
RLCPD
t
RLCPD
Figure 4 Internal Clamp Signal (CL) Timing
TEST CONDITIONS
AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70
°C, MCLK = 48MHz unless
otherwise stated (AVDD denotes the voltage applied to all AVDD pins).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
MCLK period
tPER
20.8
ns
Propagation delay
tRLCPD
15
ns
Set-up time
tRLCSU
10
ns
Hold time
tRLCH
10
ns
Notes: 1.
Internal clamp signal (CL) timing may be relative to either the falling or rising edge of MCLK depending on the setting of
control bits RESREF[3:0].
2.
Parameters are measured at 50% of the rising/falling edge.



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