WM8148 datasheet(8/43 Pages) WOLFSON

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WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

INPUT VIDEO SAMPLING (INTERNAL VSMP)

MCLK

VSMP,

OUTPUT

VIDEO

SDO,

OUTPUT

PER

VSMPPD

SDOPD

VSU

RSU

Figure 2 Input Video Timing (Internal VSMP)

TEST CONDITIONS

AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70

°C, MCLK = 48MHz unless

otherwise stated (AVDD denotes the voltage applied to all AVDD pins).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

MCLK period

tPER

20.8

MCLK duty cycle

VSMP output propagation delay

tVSMPPD

CLOAD = 10pF

SDO output propagation delay

tSDOPD

CLOAD = 10pF

Video level set-up time

tVSU

Video level hold time

tVH

Reset level set-up time

tRSU

Reset level hold time

tRH

Notes: 1.

tVSU and tRSU denote the set-up time required from when the input video signal has settled.

The reset sample point may be relative to either the rising or the falling edge of MCLK, depending on the setting of

control bits RESREF[3:0].

Parameters are measured at 50% of the rising/falling edge.

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