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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AT90SCR100 Fiches technique(PDF) 125 Page - ATMEL Corporation |
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AT90SCR100 Fiches technique(HTML) 125 Page - ATMEL Corporation |
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125 / 433 page  125 TPR0327AY–SMS–30Jan09 AT90SCR100 Figure 13-22. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) Figure 13-23 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 13-23. Timer/Counter Timing Diagram, no Prescaling Figure 13-24 shows the same timing data, but with the prescaler enabled. OCF1x OCR1x TCNT1 OCR1x Value OCR1x - 1 OCR1x OCR1x + 1 OCR1x + 2 clk I/O clk Tn (clk I/O /8) TOV1(FPWM) and ICF1(if used as TOP) OCR1x (Update at TOP) TCNT1 (CTC and FPWM) TCNT1 (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCR1x Value New OCR1x Value TOP - 1 TOP BOTTOM BOTTOM + 1 clk Tn (clk I/O /1) clk I/O |
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