MPC8533ECHXAAJB datasheet(16/116 Pages) FREESCALE

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MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

RESET Initialization

For FIFO encoded mode:

FIFO TX/RX clock frequency

≤ platform clock frequency ÷ 3.2

For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more

than 167 MHz.

4.5

Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,

see the specific section of this document.

RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8533E. Table 8 provides the RESET initialization AC timing specifications for the DDR

SDRAM component(s).

Table 9 provides the PLL lock times.

Table 8. RESET Initialization Timing Specifications1

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HREST

100

—

μs—

Minimum assertion time for SRESET

—

SYSCLKs

PLL input setup time with stable SYSCLK before HRESET

negation

100

—

μs—

Input setup time for POR configs (other than PLL config) with

respect to negation of HRESET

—

SYSCLKs

Input hold time for all POR configs (including PLL config) with

respect to negation of HRESET

—

SYSCLKs

Maximum valid-to-high impedance time for actively driven POR

configs with respect to negation of HRESET

—

SYSCLKs

Note:

1. SYSCLK is the primary clock input for the MPC8533E.

Table 9. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

Core and platform PLL lock times

—

100

μs—

Local bus PLL

—

μs—

PCI bus lock time

—

μs—

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