MPC8533ECHXAAJB datasheet(45/116 Pages) FREESCALE

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MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Local Bus

Figure 24 through Figure 29 show the local bus signals.

Figure 24. Local Bus Signals (PLL Enabled)

Table 43 describes the general timing parameters of the local bus interface at VDD = 3.3 V DC with PLL

disabled.

Table 43. Local Bus General Timing Parameters—PLL Bypassed

Parameter

Symbol1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

—

Local bus duty cycle

tLBKH/tLBK

—

Internal launch/capture clock to LCLK delay

tLBKHKT

1.2

4.9

—

Input setup to local bus clock (except LUPWAIT)

tLBIVKH1

7.4

—

4, 5

LUPWAIT input setup to local bus clock

tLBIVKL2

6.75

—

4, 5

Input hold from local bus clock (except LUPWAIT)

tLBIXKH1

–0.2

—

4, 5

LUPWAIT input hold from local bus clock

tLBIXKL2

–0.2

—

4, 5

LALE output transition to LAD/LDP output transition

(LATCH hold time)

tLBOTOT

1.5

—

Local bus clock to output valid (except LAD/LDP and LALE)

tLBKLOV1

—

1.6

—

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

tLBKHOV1

tLBKHOV2

tLBKHOV3

LSYNC_IN

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

Output (Address) Signal:

LAD[0:31]

LALE

tLBIXKH1

tLBIVKH1

tLBIVKH2

tLBIXKH2

tLBKHOX1

tLBKHOZ1

tLBKHOX2

tLBKHOZ2

Input Signal:

LGTA

tLBOTOT

tLBKHOZ2

tLBKHOX2

tLBKHOV4

LUPWAIT

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