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SC9RS08KA2 Fiches technique(PDF) 69 Page - Freescale Semiconductor, Inc |
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SC9RS08KA2 Fiches technique(HTML) 69 Page - Freescale Semiconductor, Inc |
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69 / 134 page ![]() Chapter 8 Central Processor Unit (RS08CPUV1) SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 69 BRSET n,opr8a,rel BRSET n,D[X],rel BRSET n,X,rel Branch if Bit n in Memory Set PC ← (PC) + $0003 + rel, if (Mn) = 1 — DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) IX (b0) IX (b1) IX (b2) IX (b3) IX (b4) IX (b5) IX (b6) IX (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E 00 02 04 06 08 0A 0C 0E 00 02 04 06 08 0A 0C 0E dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 0E rr 0E rr 0E rr 0E rr 0E rr 0E rr 0E rr 0E rr 0F rr 0F rr 0F rr 0F rr 0F rr 0F rr 0F rr 0F rr 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BSET n,opr8a BSET n,D[X] BSET n,X Set Bit n in Memory Mn ← 1 —— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) IX (b0) IX (b1) IX (b2) IX (b3) IX (b4) IX (b5) IX (b6) IX (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E 10 12 14 16 18 1A 1C 1E 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 0E 0E 0E 0E 0E 0E 0E 0E 0F 0F 0F 0F 0F 0F 0F 0F 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Table 8-1. Instruction Set Summary (Sheet 3 of 6) Source Form Description Operation Effect on CCR ZC 1. This is a pseudo instruction supported by the normal RS08 instruction set. 2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register. |
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