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AS4LC4M16DG-5S/XT Fiches technique(PDF) 12 Page - Austin Semiconductor |
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AS4LC4M16DG-5S/XT Fiches technique(HTML) 12 Page - Austin Semiconductor |
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12 / 25 page ![]() DRAM DRAM DRAM DRAM DRAM AS4LC4M16 AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice. 12 AS4LC4M16 Rev. 1.1 6/05 Austin Semiconductor, Inc. NOTES (Continued): 35. V IH overshoot: V IH (MAX) - V CC + 2V for a pulse width £ 3ns, and the pulse width cannot be greater than one third of the cycle rate. V IL undershoot: V IL (MIN) = -2V for a pulse width £ 3ns, and the pulse width cannot be greater then one third of the cycle rate. 36. NC pins are assumed to be left floating and are not tested for leakage. 37. Self refresh and extended refresh for the device requires that at least 4,096 cycles be completed every 128ms. 38. Self refresh version on IT temp parts only. |
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