TVP6000CPFP datasheet(23/57 Pages) TI

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2–11

µS

(7 Cycles)

13.9

µS

27.4

µS

Transition

Time: 200 ns

2 Null Characters

59.67

µS

Figure 2–11. NTSC Square Pixel Rate Closed Caption Line

10.2

µS

(7 Cycles)

13.9

µS

27.5

µS

Transition

Time: 200 ns

2 Null Characters

61.2

µS

Figure 2–12. PAL Square Pixel Rate Closed Caption Line

2.7

Clock Generation

When the CDIR pin is tied low, the TVP6000 generates the clock from the crystal connected between XTAL1

and XTAL2. Optionally, an oscillator connected to XTAL1 can also be used. The clock is used internally and

is also properly buffered and output at the LLC pin. The clock qualifying reference signal, CREF, is also an

output in this mode.

When CDIR is tied high, the LLC and CREF pins are inputs. The TVP6000 receives the clock signal from

the LLC pin and the clock qualifying reference signal from the CREF pin.

2.8

Analog Output

The TVP6000 supports simultaneous composite and S-video outputs. Additionally, the DACs may be

independently turned off via software to minimize power dissipation.

The output DACs are current sources and are optimal for driving a 37.5-

Ω load with double 75-Ω termination.

A 264-

Ω full-scale adjust resistor must be connected between the FSADJ pin and ground.

TVP6000CPFP Fiches technique(PDF) 23 Page - Texas Instruments

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