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PCM5310PAPR Fiches technique(PDF) 40 Page - Texas Instruments |
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PCM5310PAPR Fiches technique(HTML) 40 Page - Texas Instruments |
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40 / 103 page ![]() I2CTiming Diagram SDA SCL t (BUF) t (D-SU) t (SDA-R) t (SDA-F) t (P-SU) t (LOW) t (D-HD) t (S-HD) t (SCL-F) t (SCL-R) t (RS-SU) t (RS-HD) Stop Condition Start Condition t (SP) t (HI) PCM5310 SLES244 – FEBRUARY 2009 ............................................................................................................................................................................................ www.ti.com Figure 46. I2C Timing Table 29. Timing Characteristics for Figure 46 PARAMETER I2C SPECIFICATION MIN MAX UNIT fSCL SCL clock frequency Standard 100 kHz t(BUF) Bus free time between STOP and START condition Standard 4.7 µs t(LOW) SCL clock low period Standard 4.7 µs t(HI) SCL clock high period Standard 4 µs t(RS-SU) START condition setup time Standard 4.7 µs t(S-HD) START condition hold time Standard 4 µs t(D-SU) Data setup time Standard 250 ns t(D-HD) Data hold time Standard 0 900 ns t(SCL-R) SCL signal rise time Standard 20 + 0.1 CB 1000 ns Rise time of SCL signal after a repeated START t(SCL-R1) Standard 20 + 0.1 CB 1000 ns condition and after an acknowledge bit t(SCL-F) SCL signal fall time Standard 20 + 0.1 CB 1000 ns t(SDA-R) SDA signal rise time Standard 20 + 0.1 CB 1000 ns t(SDA-F) SDA signal fall time Standard 20 + 0.1 CB 1000 ns t(P-SU) STOP condition setup time Standard 4 µs CB Capacitive load for SDA and SCL line 400 pF t(SP) Suppressed spike pulse duration 25 ns 40 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM5310 |
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