CDCE62002 datasheet(22/49 Pages) TI

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Device Registers: Register 0

CDCE62002

SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com

Table 7. CDCE62002 Register 0 Bit Definitions

SPI RAM

BIT

DESCRIPTION / FUNCTION

BIT

NAME

BLOCK

Address 0

Address 1

Address 2

Address 3

INBUFSELX

Input Buffer Select (LVPECL,LVDS or LVCMOS)

EEPROM

XY(00 ) Disabled, (01) LVPECL, (10) LVDS, (11) LVCMOS

INBUFSELY

EEPROM

The VBB internal Biasing will be determined from this setting

REFSEL

Smart MUX

See specific section for more detailed description and configuration

EEPROM

Bits(2,3)

setup.

AUXSEL

EEPROM

00 – RESERVED

10 – REF_IN Select

01– AUX_IN Select

11 – Auto Select ( Reference then AUX)

ACDCSEL

Input Buffers

If Set to “1” DC Termination, If set to “0” AC Termination

EEPROM

TERMSEL

Input Buffers

If Set to “0” Input Buffer Internal Termination Enabled

EEPROM

REFDIVIDE 0

EEPROM

Reference Divider Settings.

REFDIVIDE 1

EEPROM

See specific section for more detailed description and configuration

REFDIVIDE 2

EEPROM

setup.

REFDIVIDE 3

EEPROM

EXTFEEDBACK

External Feedback to PFD from AUX Input enabled when set to “1”

EEPROM

I70TEST

TEST

Set to “0” for Normal Operation.

EEPROM

ATETEST

TEST

Set to “0” for Normal Operation.

EEPROM

LOCKW(0)

PLL Lock

Lock-detect window Bit 0

EEPROM

LOCKW(1)

PLL Lock

Lock-detect window Bit 1

EEPROM

OUT0DIVRSEL0

Output 0

Output 0 Divider Settings.

EEPROM

See specific section for more detailed description and configuration

OUT0DIVRSEL1

Output 0

EEPROM

setup.

OUT0DIVRSEL2

Output 0

EEPROM

OUT0DIVRSEL3

Output 0

EEPROM

OUT1DIVRSEL0

Output 1

Output 1 Divider Settings.

EEPROM

See specific section for more detailed description and configuration

OUT1DIVRSEL1

Output 1

EEPROM

setup.

OUT1DIVRSEL2

Output 1

EEPROM

OUT1DIVRSEL3

Output 1

EEPROM

HIPERORMANCE

Output 0 & 1

High Performance, If this Bit is set to “1”:

EEPROM

– Increase the Bias in the device to achieve Best Phase Noise on the

Output Divider

– It changes the LVPECL Buffer to Hi Swing in LVPECL.

– It increases the current consumption by 20mA (Typical)

OUTBUFSEL0X

Output 0

Output Buffer mode select for OUTPUT “0 ”.

EEPROM

(X,Y)=00:Disabled, 01:LVCMOS, 10:LVDS, 11:LVPECL

OUTBUFSEL0Y

Output 0

EEPROM

OUTBUFSEL1X

Output 1

Output Buffer mode select for OUTPUT “1 ”.

EEPROM

(X,Y)=00:Disabled, 01:LVCMOS, 10:LVDS, 11:LVPECL

OUTBUFSEL1Y

Output 1

EEPROM

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