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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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PCI4450 Fiches technique(PDF) 21 Page - Texas Instruments |
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PCI4450 Fiches technique(HTML) 21 Page - Texas Instruments |
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21 / 197 page  PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 21 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 terminal functions (continued) Table 15. CardBus PC Card Address and Data (slots A and B) TERMINAL GFN NO. GJG NO. I/O FUNCTION NAME SLOT A† SLOT B‡ SLOT A† SLOT B‡ I/O TYPE FUNCTION CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 R1 P1 N3 N2 N1 K1 K3 K2 J2 J4 H1 H3 G2 G3 F1 A2 B3 B2 D5 C4 A3 B4 C5 C6 D7 C7 B6 B7 A6 C8 A7 B8 D9 B9 A9 D10 C10 C12 D12 A13 A14 C14 A15 D14 A16 B16 C16 E17 D19 C20 D20 E18 F18 G17 E20 G18 F20 H18 G20 H20 H19 J18 J17 J19 N7 M4 M1 M6 L5 K6 J6 J5 J1 H5 H4 H1 G4 G2 G5 B3 B4 D4 D5 A4 B5 A5 F6 A6 F7 B7 D7 G7 A7 B8 E8 A8 E9 B9 A9 F9 E10 D11 E12 D12 D13 B13 E13 B14 E14 B15 A15 E16 F14 E18 F16 F15 F19 G14 G15 G18 G13 H18 H16 H14 H19 J16 J15 J18 I/O PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most significant bit. CC/BE3 CC/BE2 CC/BE1 CC/BE0 J1 F2 C3 A4 C13 A17 D18 F19 J2 G6 A2 D6 A12 E15 D19 G16 I/O CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to byte 3 (CAD31–CAD24). CPAR C2 B20 B1 C19 I/O CardBusparity. In all CardBus read and write cycles, the PCI4450 calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI4450 outputsCPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion. † Terminal name for slot A is preceded with A_. For example, the full name for terminal C2 is A_CPAR. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal B20 is B_CPAR. |
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