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BQ2012SN Fiches technique(PDF) 11 Page - Texas Instruments |
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BQ2012SN Fiches technique(HTML) 11 Page - Texas Instruments |
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11 / 20 page ![]() Command Register (CMDR) The write-only CMDR register is accessed when eight valid command bits have been received by the bq2012. The CMDR register contains two fields: I W/R bit I Command address The W/R bit of the command register is used to select whether the received command is for a read or a write function. The W/R values are: Where W/R is: 0 The bq2012 outputs the requested register contents specified by the address portion of CMDR. 1 The following eight bits should be written to the register specified by the address por- tion of CMDR. The lower seven-bit field of CMDR contains the address portion of the register to be accessed. Attempts to write to invalid addresses are ignored. Primary Status Flags Register (FLGS1) The read-only FLGS1 register (address=01h) contains the primary bq2012 flags. The charge status flag (CHGS) is asserted when a valid charge rate is detected. Charge rate is deemed valid when VSRO >VSRQ.A VSRO of less than VSRQ or discharge activity clears CHGS. The CHGS values are: Where CHGS is: 0 Either discharge activity detected or VSRO < VSRQ 1VSRO >VSRQ The battery replaced flag (BRP) is asserted whenever the potential on the SB pin (relative to VSS), VSB, falls from above the maximum cell voltage, MCV (2.25V), or rises above 0.1V. The BRP flag is also set when the bq2012 is reset (see the RST register description). BRP is reset when either a valid charge action increments NAC to be equal to LMD, or a valid charge action is de- tected after the EDV1 flag is asserted. BRP = 1 signifies that the device has been reset. The BRP values are: Where BRP is: 0 Battery is charged until NAC = LMD or dis- charged until the EDV1 flag is asserted 1VSB dropping from above MCV, VSB rising from below 0.1V, or a serial port initiated reset has occurred 11 bq2012 FLGS1 Bits 76 5 4 3 2 1 0 CHGS - -- - - - - FLGS1 Bits 76 5 4 3 2 1 0 - BRP - - - - - - CMDR Bits 76 5 4 3 2 1 0 - AD6 AD5 AD4 AD3 AD2 AD1 AD0 (LSB) CMDR Bits 76 5 4 3 2 1 0 W/R - -- - - - - TD201201.eps DQ Break 0 0 0 0 0 0 1 0 1 0 0 1 Written by Host to bq2012 CMDR = 03h Received by Host to bq2012 NAC = 65h LSB MSB LSB MSB 1 11 0 Figure 3. Typical Communication With the bq2012 |
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