BQ2012SN datasheet(9/20 Pages) TI

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Error Summary

Capacity Inaccurate

The LMD is susceptible to error on initialization or if no

updates occur.

On initialization, the LMD value in-

cludes the error between the programmed full capacity

and the actual capacity. This error is present until a

valid discharge occurs and LMD is updated (see DCR de-

scription).

The other cause of LMD error is battery

wear-out.

As the battery ages, the measured capacity

must be adjusted to account for changes in actual battery

capacity.

A Capacity Inaccurate counter (CPI) is maintained and

incremented each time a valid charge occurs (qualified

by NAC; see the CPI register description) and is reset

whenever LMD is updated from the DCR. The counter

does not wrap around but stops counting at 255. The ca-

pacity inaccurate flag (CI) is set if LMD has not been up-

dated following 64 valid charges.

Current-Sensing Error

Table 5 illustrates the current-sensing error as a func-

tion of VSR. A digital filter eliminates charge and dis-

charge counts to the NAC register when VSRO (VSR +

VOS) is between VSRQ and VSRD.

Communicating With the bq2012

The bq2012 includes a simple single-pin (DQ plus re-

turn) serial data interface. A host processor uses the in-

terface to access various bq2012 registers. Battery char-

acteristics may be easily monitored by adding a single

contact to the battery pack. The open-drain DQ pin on

the bq2012 should be pulled up by the host system, or may

be left floating if the serial interface is not used.

The interface uses a command-based protocol, where the

host processor sends a command byte to the bq2012.

The command directs the bq2012 to either store the next

eight bits of data received to a register specified by the

command byte or output the eight bits of data specified

by the command byte.

The communication protocol is asynchronous return-to-

one. Command and data bytes consist of a stream of eight

bits that have a maximum transmission rate of 333

bits/sec. The least-significant bit of a command or data

byte is transmitted first. The protocol is simple enough

that it can be implemented by most host processors using

either polled or interrupt processing. Data input from the

bq2012 may be sampled using the pulse-width capture

timers available on some microcontrollers.

Communication is normally initiated by the host proces-

sor sending a BREAK command to the bq2012.

BREAK is detected when the DQ pin is driven to a

logic-low state for a time, tB or greater. The DQ pin

should then be returned to its normal ready-high logic

state for a time, tBR. The bq2012 is now ready to receive

a command from the host processor.

The return-to-one data bit frame consists of three dis-

tinct sections.

The first section is used to start the

transmission by either the host or the bq2012 taking the

DQ pin to a logic-low state for a period, tSTRH,B. The

next section is the actual data transmission, where the

data should be valid by a period, tDSU, after the negative

edge used to start communication. The data should be

held for a period, tDV, to allow the host or bq2012 to

sample the data bit.

The final section is used to stop the transmission by return-

ing the DQ pin to a logic-high state by at least a period,

tSSU, after the negative edge used to start communication.

The final logic-high state should be held until a period, tSV,to

allow time to ensure that the bit transmission was stopped

properly. The timings for data and break communication are

given in the serial communication timing specification and

illustration sections.

Communication with the bq2012 is always performed

with the least-significant bit being transmitted first.

Figure 3 shows an example of a communication se-

quence to read the bq2012 NAC register.

bq2012 Registers

The bq2012 command and status registers are listed in

Table 6 and described in the following sections.

bq2012

Symbol

Parameter

Typical

Maximum

Units

Notes

INL

Integrated non-linearity

error

± 2

± 4

Add 0.1% per °C above or below 25°C

and 1% per volt above or below 4.25V.

INR

Integrated non-

repeatability error

± 1

± 2

Measurement repeatability given

similar operating conditions.

Table 5. Current-Sensing Error as a Function of VSR

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