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AX2000-1CSG896M Fiches technique(PDF) 84 Page - Actel Corporation

No de pièce AX2000-1CSG896M
Description  Axcelerator Family FPGAs
PDF  226 Pages
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Fabricant  ACTEL [Actel Corporation]
Site Internet  http://www.actel.com
Logo ACTEL - Actel Corporation

AX2000-1CSG896M Fiches technique(HTML) 84 Page - Actel Corporation

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Axcelerator Family FPGAs
2- 70
v2.7
Adjustable Clock Delay
Figure 2-55 illustrates using the PLL to delay the reference clock by employing one of the adjustable delay lines. In this
case, the output clock is delayed relative to the reference clock. Delaying the reference clock relative to the output
clock is accomplished by using the delay line in the feedback path.
Figure 2-55 • Using the PLL Delaying the Reference Clock
Delay Line
Delay Line
PLL
RefCLK
FB
6
/j
6
CLK1
PowerDown
Lock
CLK2
FBMuxSel
5
DividerI
DelayLine
DividerJ
LowFreq
3
Osc
÷1
133 MHz
133 MHz
/j
/i Delay
Match
/j Delay
Match



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