AT52SC1283J datasheet(49/52 Pages) ATMEL

49 / 52 page

3530B–STKD–2/4/05

AT52SC1283J/1284J [Preliminary]

52. Low-power Modes

52.1

Mode Register Set

52.2

ZZ Enable/Disable

52.3

Page Mode Enable/Disable

In asynchronous operation mode, the user has the option to toggle A0 - A3 in a random way at higher rate (20 ns vs. 70 ns)

to lower access times of subsequent reads with 16-word boundary. In synchronous mode, this option has no effect. The

maximum page length is 16 words.

Please note that as soon as Page Mode is enabled the CS1 low time restriction applies. This means that the CS1 signal

must not be kept low longer than tRC(tWC) = 10 µs.

52.4

MRS Update

Note:

The register update takes place on the rising edge of ZZ. Once the register is updated, the next time ZZ goes low, without any

updates to the register starting within the t

ZZWE max time of 1 µs, the part will refresh the array selected. The data bus is a don’t

care when ZZ is low during the register updates.

A20 - A8 (32M)

A21 - A8 (64M)

A3 - A0

Page Mode

Enable/Disable

Type

Deep Power-down Enable

DPD Disable (Default)

Note:

If the register is written to enable the Deep Power-down, the part will go into Deep Power-down during the following time that

ZZ is driven low and there is no MRS update. When ZZ is driven high, all of the register settings will return to default state for

the part (i.e. full array refresh, Deep Power-down Disabled).

Type

Page Mode Disabled (Default)

Page Mode Enabled

Address

PCS1

PUB, PLB

PWE

ZWE

Complete

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