7733 datasheet(258/940 Pages) RENESAS

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SERIAL

I/O

7733 Group User’s Manual

8–55

8.4 Clock asynchronous serial I/O (UART) mode

Fig. 8.4.8 Example of transmit timing when data is transferred in 8 bits (When parity is enabled, one

____

stop bit, and CTS function is selected)

D0 D1 D2 D3 D4 D5 D6 D7

PSP

D0 D1

D0 D1 D2 D3 D4 D5 D6 D7

TENDi

TxDi

“0”

“1”

“0”

“1”

“0”

“1”

“0”

“1”

“L”

“H”

CTSi

Stopped because CTS pin’s level is “H.”

Transmit enable bit

Transmission buffer

empty flag

Transmission register

empty flag

Start bit

Stop bit

Data is set in UARTi transmission buffer register.

Transfer clock

The above timing diagram is applied when

the following conditions are satisfied:

q Parity is enabled.

q 1 stop bit

q CTS function is selected.

TC = 16(n + 1)/fi or 16(n + 1)/fEXT

fi : BRGi’s count source frequency (f2, f16, f64, or f512)

fEXT : BRGi’s count source frequency (external clock)

n : Value set to BRGi

← UARTi transmission buffer register

Stopped because transmit enable bit = “0”

UARTi transmission

interrupt request bit

Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software.

Parity bit

TENDi : Next transmit conditions are checked when this signal level becomes “H.”

(TENDi is an internal signal. Accordingly, it cannot be read from the external.)

UARTi transmission register

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