7733 datasheet(506/940 Pages) RENESAS

506 / 940 page

7733 Group User’s Manual

18–40

LOW VOLTAGE VERSION

18.6.5 Ready generating circuit example

When validating “wait” only for a certain area (for example, ROM area) in Figures 18.6.3 to 18.6.8, use the

ready function.

Figure 18.6.9 shows a ready generating circuit example.

Fig. 18.6.9 Ready generating circuit example

M37733MHLXXXHP

CS1

A8 to A23

(D0 to D15)

A0 to A7

AC74

RDY

AC32

AC04

Address bus

Data bus

Address

latch circuit

Address

decode

circuit

CS2

Wait generated by the ready function is

inserted only to an area where

accessed by Signal CS 2.

Circuit conditions : f(X IN)

≤ 10.8 MHz, no wait,

CS2

RDY

td(E- 1)

tsu(RDY- 1)

Propagation delay time of AC32

(Max. : 11.9 ns)

V Condition to satisfy the relationship of

tsu(RDY- 1)

≥ 80 ns in

the left timing chart is t

Accordingly, when f(X IN)

≤ 10.8 MHz, this

example satisfies the relationship of

tsu(RDY- 1)

≥ 80 ns.

: Wait generated by the ready function

, or

f(XIN)

f(XCIN)

VCC = 3.0 to 5.5 V

≥ 91.9 ns.

18.6 Applications

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