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HD64F2149YV Fiches technique(PDF) 924 Page - Renesas Technology Corp |
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HD64F2149YV Fiches technique(HTML) 924 Page - Renesas Technology Corp |
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924 / 1075 page ![]() Appendix B Internal I/O Registers Rev. 3.00 Jan 18, 2006 page 896 of 1044 REJ09B0280-0300 CRA—DTC Transfer Count Register A H'EC00–H'EFFF DTC 15 Unde- fined — Bit Initial value Read/Write 14 Unde- fined — 13 Unde- fined — 12 Unde- fined — 11 Unde- fined — 10 Unde- fined — 9 Unde- fined — 8 Unde- fined — 7 Unde- fined — 6 Unde- fined — 5 Unde- fined — 4 Unde- fined — 3 Unde- fined — 2 Unde- fined — 1 Unde- fined — 0 Unde- fined — CRAH CRAL Specifies the number of DTC data transfers CRB—DTC Transfer Count Register B H'EC00–H'EFFF DTC 15 Unde- fined — Bit Initial value Read/Write 14 Unde- fined — 13 Unde- fined — 12 Unde- fined — 11 Unde- fined — 10 Unde- fined — 9 Unde- fined — 8 Unde- fined — 7 Unde- fined — 6 Unde- fined — 5 Unde- fined — 4 Unde- fined — 3 Unde- fined — 2 Unde- fined — 1 Unde- fined — 0 Unde- fined — Specifies the number of DTC block data transfers |
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