M32CSLASH8A datasheet(99/372 Pages) RENESAS

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M32C/8A Group

9. Clock Generation Circuits

Rev.1.00

Jul 15, 2007

Page 82 of 352

REJ09B0385-0100

Table 9.3

Bit Settings to Use PLL Clock as CPU Clock Source

Figure 9.12

Procedure to Use PLL Clock as CPU Clock Source

Multiplication

factor

PLC0 Register

PLC1 Register

PLL Clock

PLC02 bit

PLC01 bit

PLC00 bit

PLC12 bit

011

fPLL = 2 × fXIN

fPLL = 3 × fXIN

8/3

100

fPLL = 8/3 × fXIN

fPLL = 4 × fXIN

Start

End

Set registers PLC0 and PLC1

PRCR register: PRC0 bit = 1

PLC0 register: PLC07 bit = 1

CM1 register : CM17 bit = 1

PRC0 bit = 0

Wait for tsu(PLL)

Enable writing to registers associated with clocks

CM2 register: CM21 bit = 0

CM0 register: CM07 bit = 0

Select the main clock as the CPU clock source

(※Set after a main clock oscillation stabilizes)

Select the multiplication factor for the PLL clock

(※Set registers PLC0 and PLC1 simultaneously in 16-bit units)

　 PLC1

PLC0

Multiplication factor for PLL clock

00000010 01010011b

× 6/2 = 3

00000010 01010100b

× 8/2 = 4

00000110 01010011b

× 6/3 = 2

00000110 01010100b

× 8/3 = 2.66

PLL runs

Select the PLL clock as the clock source for the CPU clock

and peripheral function clock

Disable writing to registers associated with clocks

Wait for PLL frequency synthesizer to stabilize

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