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HD404339FS Fiches technique(PDF) 56 Page - Renesas Technology Corp

No de pièce HD404339FS
Description  microcomputer with large-capacity memory designed to
PDF  80 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD404339FS Fiches technique(HTML) 56 Page - Renesas Technology Corp

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HD404339 Series
54
Transmit clock errors are detected as illustrated in figure 42.
Transfer completion
(IFS
1)
Interrupts inhibited
IFS
0
SMR write
IFS = 1
Transmit clock
error processing
Normal
termination
←
←
Yes
No
Transmit clock error detection flowchart
Transmit clock error detection procedure
State
SCK pin (input)
Transmit clock
wait state
Transfer state
Transfer state
Transmit clock wait state
Noise
Transfer state has been
entered by the transmit
clock error. When SMR
is written, IFS is set.
Flag set because octal
counter reaches 000.
Flag reset at
transfer completion.
SMR write
IFS
12
3
4
56
78
Figure 42 Transmit Clock Error Detection



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