M24M01-R_08 datasheet(25/36 Pages) STMICROELECTRONICS

25 / 36 page

M24M01-R, M24M01-W, M24M01-HR

DC and AC parameters

25/36

Table 14.

AC characteristics at 1 MHz (M24M01-HR)

Test conditions specified in Table 7

Symbol

Alt.

Parameter

Min.

Max.

Unit

fSCL

Clock frequency

MHz

tCHCL

tHIGH

Clock pulse width high

300

tCLCH

tLOW

Clock pulse width low

400

tXH1XH2

(1)

Input rise/fall time values recommended by the Fast-mode Plus I²C-bus specification. The M24xxx devices

accept longer input rise/fall times provided that these rise/fall times are compatible with all other timing

conditions defined in this AC table.

Input signal rise time

300

tXL1XL2

(1)

Input signal fall time

120

tQL1QL2

(2)(3)

Characterized only, not tested in production.

The SDA(out) rise time is not defined by the M24xxx, it is defined by the application pull-up resistor

(connected on the SDA line) and, therefore, it is not specified in this table.

SDA (out) fall time

120

tDXCH

tSU:DAT

Data in setup time

tCLDX

tHD:DAT Data in hold time

tCLQX

tDH

Data out hold time

tCLQV

(4)(5)

To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC, assuming

that the Rbus × Cbus time constant is less than 150 ns (as specified in Figure 5).

tAA

Clock low to next data valid (access time)

500

tCHDL

(6)

For a reStart condition, or following a Write cycle.

tSU:STA

Start condition setup time

250

tDLCL

tHD:STA Start condition hold time

250

tCHDH

tSU:STO Stop condition setup time

250

tDHDL

tBUF

Time between Stop condition and next

Start condition

500

tWR

Write time

tNS

(2)

Pulse width ignored (input filter on SCL

and SDA)

-50

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