STPCCLIENT datasheet(28/48 Pages) STMICROELECTRONICS

28 / 48 page

STRAP OPTION

28/48

Issue 1.7 - February 8, 2000

Note; Setting of Strap Options MD [15:2] have no

effect on the DRAM Controller but are purely

meant for software issues. i.e. Readable in a reg-

ister.

3.1 Power on strap registers description

3.1.1 Strap register 0 Index 4Ah (Strap0)

Bits 7-0; This register reflect the status of pins

MD[7:0] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

Note that the SIMM speed and type information

read here is meant only for the software and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

This register defaults to the values sampled on

MD[7:0] pins after reset.

3.1.2 Strap register 1 Index 4Bh (Strap1)

Bits 7-0; This register reflect the status of pins

MD[15:8] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

Note that the SIMM speed and type information

read here is meant only for the software and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

This register defaults to the values sampled on

MD[15:8] pins after reset.

3.1.3 Strap register 2 Index 4Ch (Strap2)

Bits 4-0; This register reflect the status of pins

MD[20:16] respectively.They are use by the chip

as follows:

Bit 4-2; Reserved.

Bit 1; This bit reflects the value sampled on

MD[17] pin and controls the PCI clock output as

follows:

0: PCI clock output = HCLK / 2

1: PCI clock output = HCLK / 3.

Bit 0; Reserved.

This register defaults to the values sampled on

MD[20:16] pins after reset.

MD38

Reserved

MD39

Reserved

MD40

Reserved

MD41

Reserved

MD42

Reserved

MD43

Reserved

Memory

Data

Lines

Refer to

Designation

Location

Actual

Settings

Set to ’0’

Set to ’1’

Bit Sampled

Description

Bit 7

SIMM 0 DRAM type

Bits 6-5

SIMM 0 speed

Bit 4

SIMM 1 DRAM type:

Bits 3-2

SIMM 1 speed

Bit 1

Reserved

Bit 0

Reserved

Bit Sampled

Description

Bit 7

SIMM 2 DRAM type

Bits 6-5

SIMM 2 speed

Bit 4

SIMM 3 dram type

Bits 3-2

SIMM 3 speed

Bit 1

Reserved

Bit 0

Reserved

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