STLS2F02 datasheet(14/49 Pages) STMICROELECTRONICS

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Interface description

STLS2F02

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2.9

Clock signals

Table 8 details the STLS2F02 chip clocks. The processor has three system input clock

signals. (SYSCLK, MEMCLK and PCI_CLK). TESTCLK is only used for chip test.

The CPU core clock and DDR2 control clock are generated separately by the PLL using

SYSCLK and MEMCLK. The frequency division is controlled by CLKSEL. For further

information about the division factor, see Table 9 and Table 10. MEMCLK frequency can

also be configured through control register CR88 except pins CLKSEL [9:5]. Please refer to

Table 8.

Clock signals

Name

Input/output

Description

SYSCLK

System input clock, which drives the built-in PLL to

generate core clock. It also used as clock of system reset

circuit

MEMCLK

DDR2 controller input clock, which is used by the built-in

PLL to generate DDR2 control clock

CLKSEL[4:0]

PLL frequency division control signal of core clock, see

Table 9

CLKSEL[9:5]

PLL frequency division control signal of DDR2 controller

clock, see

Table 10

PCI_CLK

Clock for PCI and local bus interface.

Table 9.

Processor internal/external frequency configuration

CLKSEL[4:0]

Multi.

factor

Input frequency

range (MHz)

CLKSEL[4:0]

Multi.

factor

Input frequency

range (MHz)

11xxx

10000

2.25

88.9~177.8

01100

6.5

61.5~123.1

10001

2.5

80.0~160.0

01101

57.1~114.3

10010

2.75

72.7~145.5

01110

7.5

53.3~106.7

10011

66.7~133.3

01111

50.0~100.0

10100

3.25

61.5~123.1

00000

88.9~177.8

10101

3.5

57.1~114.3

00001

80.0~160.0

10110

3.75

53.3~106.7

00010

72.7~145.5

10111

50.0~100.0

00011

66.7~133.3

01000

4.5

88.9~177.8

00100

61.5~123.1

01001

80.0~160.0

00101

57.1~114.3

01010

5.5

72.7~145.5

00110

53.3~106.7

01011

66.7~133.3

00111

50.0~100.0

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