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STA335BWS Fiches technique(PDF) 40 Page - STMicroelectronics |
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STA335BWS Fiches technique(HTML) 40 Page - STMicroelectronics |
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40 / 68 page ![]() Register description STA335BWS 40/68 2.1 channels, two fullbridge + one external full bridge (OCFG = 10): " DDX1A ' OUT1A " DDX1B ' OUT1B " DDX2A ' OUT2A " DDX2B ' OUT2B " DDX3A ' OUT3A " DDX3B ' OUT3B " EAPD ' OUT4A " TWARN OUT4B " DDX1A/1B configured as ternary " DDX2A/2B configured as ternary " DDX3A/3B configured as ternary " DDX4A/4B is not used In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed. In this configuration the PWM slot phase is the following as shown in the next figures: Figure 15. 2.1 channels (OCFG = 10) PWM slots 6.6.2 Invalid input detect mute enable Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the signals are perceived as invalid. OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B Bit R/W RST Name Description 2R/W 1 IDE Setting of 1 enables the automatic invalid input detect mute |
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