STA323W datasheet(48/77 Pages) STMICROELECTRONICS

48 / 77 page

STA323W

48/77

7.6

Configuration register F (address 0x05)

7.6.1

Output configuration selection

Setting the IDE bit enables this function, which looks at the input I2S data and clocking and

automatically mutes all outputs if the signals are invalid.

Detects loss of input MCLK in binary mode and outputs 50% duty cycle to prevent audible

noise when input clocking is lost.

EAPD

PWDN

ECLE

Reserved

BCLE

IDE

OCFG1

OCFG0

10111

Table 43.

Output configuration selection

Bit

R/W

RST

Name

Description

1:0

OCFG[1:0]

00: 2-channel (full-bridge) power, 1-channel DDX is default

Table 44.

Output configuration selections

OCFG[1:0]

Output power configuration

2 channel (full-bridge) power, 1 channel DDX:

1A/1B

◊ 1A/1B

2A/2B

◊ 2A/2B

2(half-bridge).1(full-bridge) on-board power:

◊ 1A

Binary

◊ 1B

Binary

3A/3B

◊ 2A/2B Binary

Reserved

1 channel mono-parallel:

◊ 1A/1B

◊ 2A/2B

Table 45.

Invalid input detect mute enable

Bit

R/W

RST

Name

Description

2RW

IDE

0: disabled

1: enabled

Table 46.

Binary clock loss detection enable

Bit

R/W

RST

Name

Description

3RW

BCLE

0: disabled

1: enabled

STA323W Fiches technique(PDF) 48 Page - STMicroelectronics

STA323W Fiches technique(HTML) 48 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Fiches technique Télécharger

Lien URL