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STP24DP05 Fiches technique(PDF) 16 Page - STMicroelectronics |
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STP24DP05 Fiches technique(HTML) 16 Page - STMicroelectronics |
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16 / 26 page ![]() Feature description STP24DP05 16/26 Figure 12. Detection circuit 7.3 Phase one: “entering in detection mode” From the “normal mode” condition the device can switch to the “error detection mode“ by a DM PIN set to LOW or a logic sequence on the OE-R/DM and LE/DM pins as showed in the following table and diagram: Figure 13. EDM timing diagram using DM pin 16 STP24DP05 24 23 Table 12. SPI sequence to enter in detection mode - truth table CLK 1°2°3°4° 5° OE-R/DM H L HHH LE/DM LLL H L |
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