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STLVD111 Fiches technique(PDF) 1 Page - STMicroelectronics |
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STLVD111 Fiches technique(HTML) 1 Page - STMicroelectronics |
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1 / 12 page ![]() 1/12 December 2002 s 100ps PART-TO PART SKEW s 50ps BANK SKEW s DIFFERENTIAL DESIGN s MEETS LVDS SPEC. FOR DRIVER OUTPUTS AND RECEIVER INPUTS s REFERENCE VOLTAGE AVAILABLE OUTPUT VBB s LOW VOLTAGE VCC RANGE OF 2.375V TO 2.625V s HIGH SIGNALLING RATE CAPABILITY (EXCEEDS 622MHz) s SUPPORT OPEN, SHORT AND TERMINATED INPUT FAIL-SAFE (LOW OUTPUT STATE) s PROGRAMMABLE DRIVERS POWER OFF CONTROL DESCRIPTION The STLVD111 is a low skew programmable 1 to 10 differential LVDS driver, designed for clock distribution. The select signal is fanned out to 10 identical differential outputs. The STLVD111 is provided with a 11 bit shift register with a serial in and a Control Register. The purpose is to enable or power off each output clock channel and to select the clock input. The STLVD111 is specifically designed, modelled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device. The net result is a dependable guaranteed low skew device. The STLVD111 can be used for high performance clock distribution in 2.5V systems with LVDS levels. Designers can take advantage of the device’s performance to distribute low skew clocks across the backplane or the board. ORDERING CODES Type Temperature Range Package Comments STLVD111BF -40 to 85 °C TQFP32 (Tray) 250 parts per Tray STLVD111BFR -40 to 85 °C TQFP32 (Tape & Reel) 2400 parts per reel STLVD111 PROGRAMMABLE LOW VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK DRIVER TQFP32 |
Numéro de pièce similaire - STLVD111 |
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Description similaire - STLVD111 |
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