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STULPI01ATBR Fiches technique(PDF) 25 Page - STMicroelectronics |
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STULPI01ATBR Fiches technique(HTML) 25 Page - STMicroelectronics |
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25 / 44 page ![]() STULPI01A - STULPI01B Block description 25/44 6.18.7 High speed mode entry In high speed mode, the internal 480 MHz clock is generated by the DLL, which must be calibrated any time device enters high speed mode by writing '00' to the XcvrSel field in the Function Control register. During the DLL calibration it is not possible to accept any commands, therefore to avoid any communication problems with the controller the clock on the ULPI interface is stopped. See Figure 10 for more information. Figure 8. Start-up sequence Figure 9. RESETn behavior |
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